This invention relates generally to the fabrication of integrated circuits.
To increase performance of NMOS and PMOS deep sub-micron transistors in CMOS technology, current state-of-the-art technology uses compressive stress in the channel of the PMOS transistors, and tensile stress in the case of NMOS transistors.
Existing technologies that use strained channels are subject to a number of limitations. For example, polysilicon depletion may occur in the PMOS devices. In addition, tensile strain may arise in the PMOS devices. Remaining tensile strain degrades hole mobility in the PMOS devices.
Thus, there is a need for a better complementary metal oxide semiconductor process and particularly one which improves the performance of PMOS devices.